Differential dc amplifier

ABSTRACT

1. IN A TRANSISTOR DIFFIERENTIAL AMPLIFIER HAVING: A FIRST AND A SECOND CONNECTION MEANS FOR CONNECTION TO A POTENTIAL BIAS SOURCE, A PAIR OF INPUT TRANSISTORS FOR RECEIVING AN IMPUT SIGNAL BETWEEN THE BASE ELECTRODES THEREOF, AND A COMMON MODE NEGATIVE FEEDBACK PATH, SAID PATH INCLUDING A NEGATIVE FEEDBACK RESISTOR CONNECTED TO SAID SECOND CONNECTION MEANS, THE IMPROVEMENT COMPRISING: A PAIR OF DYNAMIC LOAD TRANSISTORS EACH HAVING THE EMITTER-COLLECTOR CIRCUITS THEREOF CONNECTED IN SERIES WITH THE EMITTER-COLLECTOR CIRCUITS OF A DIFFERENT ONE FOR SAID INPUT TRANSISTORS AND CONNECTED THROUGH A VARIABLE RESISTANCE   TO SAID FIRST CONNECTION MEANS, A BIAS RESISTOR CONNECTED BETWEEN SAID FIRST CONNECTION MEANS AND SAID NEGATIVE FEEDBACK RESISTOR TO THEREBY PROVIDE A NEGATIVE FEEDBACK BIAS LOOP, AND MEANS CONNECTING THE BASE ELECTRODES OF SAID DYNAMIC LOAD TRANSISTORS IN PARALLEL WITH EACH OTHER AND TO SAID BIAS RESISTOR.

y 1972 o. R. MCGRAW ETAL Re. 27,351

DIFFERENTIAL DC AMPLIFIER I Original Filed Sept. 14, 1966 1 N VEN TORSDONALD R. MCGRAW JERALD G. GRAEME BY ATTORNEYS United States Patent 27351 DIFFERENTIAI: DC AMPLIFIER Donald R. McGraw and Jerald G. Graeme,Tucson, Ariz.,

assignors to Burr-Brown Research Corporation, Tuc- Matter enclosed inheavy brackets appears in the original patent but forms no part of thisreissue specification; matter printed in italics indicates the additionsmade by reissue.

The present invention relates to transistor differential amplifiers, andmorespecificallyyto differential amplifiers for use in high performance,low level applications.

The substantial increase in the utilization of transistorized DCamplifiers has given rise to problems of environmental nature heretoforerequiring compensation in the design of the transistor circuits. Thedesirability of high input impedance and low or substantially zero inputoffset voltage drift with temperature has resulted 'in prior art circuitdesigns that are expensive to fabricate using integrated circuittechniques. characteristically, DC transistorized differentialamplifiers require resistances ofhig'h value in the emitter-collectorcircuits of the' fitst stage; these high resistancesare difficult andexpensive reform and are therefore not particularly adaptable tointegrated circuit fabrication techniques.

The wide variety of applications in which transistorized differential DCamplifiers are used also gives rise to the temperature variation of theparameters of the transistors. It has been found that operation oftransistors of the same type at the same base-to-emitter bias voltagewill result in the temperature coefiicients of the base-to-emittervoltage being approximately equal. The conclusion drawn in the prior artthus led to the compensation of temperature deviation of the transistorsthrough the utilization of different collector currents in thetransistors of the input stage in an attempt to maintain'a constantbase-toemitter bias voltage. The proposed self-compensation 'hasresulted in prior art circuits utilizing complicated compensationschemes incorporating additional resistors. These methods compensatefor, but do not eliminate, the'difference between the base emittervoltages ofthe input transistors. The thermal voltage drift of the inputtransistors is therefore not improved "to the extent possible'if thedifference were eliminated. It is therefore an object of thepresentihventiohto provide a differential amplifier without highresistors and therefore capable of economical reproduction by integratedcircuit techniques.

It is another object of the present invention to provide a transistordifferential amplifier wherein the typically high collector resistanceofthe first stage is eliminated.

provide a transistor differential amplifier having improved thermalvoltage drift of the input transistors.

It is another object of the present invention to provide a transistordifferential amplifier in which cancellation of the input offset voltageis utilized to decrease the drift of offset voltage with temperaturevariations.

These and other objects of the present invention will become apparent tothose skilled in the art as the description thereof proceeds.

The embodiment chosen for illustration, shown in the drawing, is atwo-stage differential amplifier having a current source transistorconnected to the emitters of the first stage and incorporating a commonmode negative feedback loop. In the description of the drawing, the

terminology common mode and differential mode shall have meaningsordinarily understood by those in the art; that is, common mode isdefined as half the sum of the voltages applied to the input terminals,and the differential mode is defined as half the difference of thevoltages applied to the input terminals.

Referring to the drawing, input terminals 10 and 11 are connected to thebase electrodes of transistors T1 and T2 respectively. Transistors T1and T2 comprise the input stage of the differential amplifier and havetheir emitter electrodes connected in parallel to the collectorelectrode of an emitter current source transistor T3. The collectorelectrodes of transistors T1 and T2 are each connected to the collectorelectrodes of dynamic load transistors T4 and T5 respectively. Thedynamic load transistors are complementary to their respective connectedinput transistors T1 and T2. The dynamic load transistors provide acurrent source to the input transistors and also provide impedances ofseveral hundred thousand ohms while nevertheless readily permittingeconomic integrated circuit fabrication.

The se-cond-stage transistors T6 and T7 are each connected via theirrespective base electrodes to the collector electrodes of one of theinput transistors. The emitter electrodes of the transistors T6 and T7are connected together and to a voltage divider comprising resistances14 and 15. The collector electrodes of transistors T6 and T7 areconnected through resistances 16 and 17 respectively to one terminal 20which, as indicated in the drawing is connected to a suitable positivepotential bias source. The collector electrodes of transistors T6 and T7also are connected to output terminals 21 and 22.

The emitter electrodes of transistors T4 and T5 are connected to thebias potential source through a potentiometer 26 which provides, ineffect, a variable resistance in 'each of the respective emittercircuits. The poteniometer includes a resistance 27 the ends of whichare each connected to the emitters of transistors T4 and T5respectively. A wiper arm 28, connected to the terminal 20, contacts theresistor 27 to thereby vary the current supplied to theemitter-collector circuits of the transistors T4 to theemitter-collector circuits of the transistors T1 and T2; the emitterelectrode of transistor T3 is connected through resistor 34 to a secondterminal 35 which, as shown in FIGURE 1, is connected to the negativeside of the bias potential source. Since the constant current source L.transistor T3 operates to regulate the total current flowing through thefirst stage of the amplifier, a feedback loop may be provided byconnecting the base electrode of transistor T3 to the junction of theresistors 14 and 15. In this manner, a common mode negative feedbackloop is formed which includes the emitter-collector circuits of It 1sstill another ob ect of the present invention to transistors T1 and T2,the base-emitter circuits of transistors T6 and T7, and the resistor 14.The common mode negative feedback acts to improve the discriminationfactor (defined as the ratio of differential mode to comu mon mode gain)and also improves the common mode rejection factor (defined as the ratioof the common mode voltage input to the differential mode voltage inputto produce the same output voltage). The differential ampli- I isconnected between the resistor 39 and the terminal 20; Whereas, resistor39 is connected'between the resistor 38 and the emitter electrodes oftransistors T6 and T7. The negative feedback bias loop thus providedincludes the emitter-collector circuits of transistors T1 and T2 as wellas T4 and T5, the potentiometer 26, the voltage divider resistors 38 and39, the resistor 14, and the base-collector circuit of the transistorT3. It may be noted that the negative feedback bias loop shares theresistance 14 and transistor T3 with the common mode negative feedbackloop.

The operation of the circuit of the present invention may best bedescribed by assuming the bias voltage on the collector electrodes oftransistors T1 and T2- to be reduced to a value lower than desired. Theresulting drop in the bias voltage causes reduced current flow throughtransistors T6 and T7 with a subsequent reduced voltage drop through thevoltage divider comprising resistors 14 and 15. The lower voltage dropacross the voltage divider will result in reduced current throughtransistor T3 and therefor reduce current in the collector circuits oftransistors T1 and T2. A prior art design, incorporating a passivecollector load on the transistors T1 and T2 could only attempt tocompensate for this deficiency; however, the low bias voltage on thecollector of transistors T1 and T2 (resulting in the decreased voltagedrop across resistors 14 and .15) effectively lowers the voltage at thejunction of resistors 38 and 39, causing an increase in the current flowthrough the emitter-collector circuits of transistors T4 and T5. Thisincrease in current subsequently restores the bias voltage on thecollectors of T1 and T2. Thus, it may be seen that the uniquecombination of the common mode negative feedback loop and the negativefeedback bias loop results in a cooperative effort to maintain thecollector bias voltage constant. The constancy of this voltage ismaintained without the utilization of large resistances heretoforeincorporated in prior art designs; the utilization of transistors T4 andT render the present design feasible for construction usingmicroelectronic integrated circuit techniques.

The temperature dependence of the amplifier is improved by maintainingthe base-to-emitter voltages of transistors T 1 and T2 equal. The equalbias voltages are forced on transistors T1 and T2 by adjusting the wiperarm 28 of the potentiometer 26-; as indicated previously, positioning ofthe wiper arm '28 unbalances the currents flowing through the respectiveemitter-collector circuits of transistors T1, T2, T4 and T5. Thebase-to-emitter voltages on transistors T1 and T2 may thus be forced tobe equal to insure minimum input offset voltage drift with temperature.

-It will be obvious to those skilled in the art that many modificationsof the present circuit may be made without departing from the spirit andscope of the invention. For example, the utilization of NPN or PNPtransistors may, in certain applications, be a matter of choice;similarly the number of stages in any particular amplifier may bedictated by various considerations not discussed in con nection with thedrawing. It is therefore intended that the present invention be limitedonly by the scope of the claims appended hereto.

We claim:

1. In a transistor differential amplifier having: a first and a secondconnection means for connection to a potential bias source, a pair ofinput transistors for receiving an imput signal between the baseelectrodes thereof, and a common mode negative feedback path, said pathincluding a negative feedback resistor connected to said secondconnection means, the improvement comprising: a pair of dynamic loadtransistors each having the emitter-collector circuits thereof connectedin series with the emitter-collector circuits of a different one of saidinput transistors and connected [through a variable resistance] to saidfirst connection means; a bias resistor connected between said firstconnection means and said negative feedback resistor to thereby providea negative feedback bias loop; and means connecting the base electrodesof said dynamic load transistors in parallel with each other and to saidbias resistor.

2. In a transistor differential amplifier having: a first and a secondconnection means for connection to a potential bias source, a pair ofinput transistors for receiving an input signal between the baseelectrodes thereof, and a common mode negative feedback path, said pathincluding a negative feedback resistor connected to said secondconnection means, the improvement comprising: a pair of dynamic loadtransistors each having the emitter-collector circuits thereof connectedin series with the emitter-collector circuits of a different oneof saidinput transistors and connected [through a variable resistance] to saidfirst connection means; a voltage divider connected between said firstconnection means and said negative feedback resistor to thereby providea negative feedback bias loop; and means connecting the base electrodesof said dynamic load transistors in parallel with each other and to saidvoltage divider.

3. The circuit set forth in claim 2 wherein said dynamic loadtransistors are complementary types relative to said input transistors.

-4. The circuit set forth in claim 2 wherein said input transistors areNPN type and said dynamic load transistors are PNP type.

5. The circuit set forth in claim 2 wherein said variable resistancecomprises a potentiometer having a resistance the opposite ends of whichare connected to the emitter-collector circuits of dilferent dynamicload transistors and having a wiper arm connected to said firstconnection means.

6. In a two-stage transistor differential amplifier having: a first anda second connection means for connection to a potential bias source, apair of input transistors for receiving an input signal between the baseelectrodes thereof, a pair of second-stage transistors having the baseelectrodes thereof each connected to an emitter-collector circuit of adifferent one of said input transistors, a common mode negative feedbackpath, said path including a negative feedback resistor connected to saidsecond connection means, means connecting the emitter-collector circuitsof said second-stage transistors in parallel between said firstconnection means and said negative feedback resistor, the improvementcomprising: a pair of dynamic load transistors each having theemitter-collector circuits thereof connected in series with theemittercollector circuits of a different one of said input transistorsand connected through a variable resistance to said first connectionmeans; a voltage divider connected between said first connection meansand said negative feedback resistor to thereby provide a negativefeedback bias loop; and means connecting the base electrodes of saiddynamic load transistors in parallel with each other and to said voltagedivider.

7. The circuit set forth in claim 6 wherein said dynamic loadtransistors are complementary types relative to said input transistors.

*8. The circuit set forth in claim 6 wherein said input transistors areNPN type and said dynamic load transistors are PNP type.

9. The circuit set forth in claim 6 wherein the variable resistancecomprises a potentiometer having a resistance the opposite ends of whichare connected to the emittercollector circuits of different dynamic loadtransistors and having a wiper arm connected to said first connectionmeans. I Q

10. A transistor amplifier comprising. a first and a second connectionmeans for connection to a potential bias source, a pair of inputtransistors for receiving an input signal between the base electrodethereof; a pair of second-stage transistors having the base electrodesthereof each connected to a collector electrode of a different one ofsaid input transistors; a common mode negative feedback voltage dividerconnected between the emitter electrodes of said second-stagetransistors and said second connection means; an emitter current sourcetransistor having a collector electrode connected to the emitterelectrodes of said input transistors, an emitter electrode connectedthrough a resistor to said second connection means, and a base electrodeconnected to said common mode negative feedback voltage divider; a pairof dynamic load transistors, complementary in type to said inputtransistors, each having a collector electrode connected to thecollector electrode of a different one of said input transistors; apotentiometer having a resistance the opposite ends of which areconnected to the emitters of difierent dynamic load transistors andhaving a wiper arm connected to said first connections means; a negativefeedback bias voltage divider connected between said first connectionmeans and the emitter electrodes of said secondstage transistors tothereby provide a negative feedback bias loop; means connecting the baseelectrodes of said References Cited The following references, cited bythe Examiner, are of record in the patented file of this patent or theoriginal patent.

UNITED STATES PATENTS 3,275,944 9/1966 Lavin 330-69 X ROY LAKE, PrimaryExaminer L. J. DAHL, Assistant Examiner US. Cl. X.R.

